mesi protocol

For any given pair of caches, the permitted states of a given cache line are as follows:

	M	E	S	I
M	X	X	X	O
E	X	X	X	O
S	X	X	O	O
I	O	O	O	O

Curstate	Operation	NextState	SOther Core
INVALID	Read	case EXCLUSIVE if other core is INVALID	INVALID (No operation)
		case SHARED if other core contains data	SHARED (no operation) MODIFIED -> Flush -> SHARED EXCLUSIVE -> SHARED
INVALID	Write	MODIFIED	INVALID (no operation) SHARED -> INVALID MODIFIED -> Flush -> INVALID EXCLUSIVE -> INVALID
EXCLUSIVE	Read	EXCLUSIVE	INVALID (No operation)
EXCLUSIVE	Write	MODIFIED	INVALID (No operation)
SHARED	Read	SHARED	INVALID (no operation) SHARED (no operation)
SHARED	Write	MODIFIED	INVALID (no operation) SHARED -> INVALID
MODIFIED	Read	MODIFIED	INVALID (No operation)
MODIFIED	Write	MODIFIED	INVALID (No operation)

Reference: https://github.com/Yefei100/Cache_coherence_protocol/blob/master/main.cc

run riscv on qemu-system-riscv32

Sightly modify riscv.ld (download riscv.ld):

1. Ensure the rom starts from 0x80000000. (matched with virt machine type)
2. Set _init as entry function, place .text.init at 0x80000000.
3. Add stack pointer initial location
   

In start.S, add _init function to setup sp and gp register:

.extern _start
.section .text.init
        .globl _init
_init:
        lui gp, %hi(ROM_START)     #_rom_start = 0x80000000 in linker script
        addi gp, gp, %lo(ROM_START)
        lui sp, %hi(init_sp)
        addi  sp, sp, %lo(init_sp)
        j  _start

riscv-none-elf-gcc -o helloworld.elf -march=rv32imad start.S helloworld.c -T riscv.ld

riscv-none-elf-objdump -D helloworld.elf > helloworld.S

qemu-system-riscv32 --machine virt -bios helloworld.elf -m 128M -nographic -singlestep -d exec,int,cpu 2>&1 | tee ins.log

Add cpu option above can dump the register value per step.

printf(...) require override _write() which could be found in newlib/libgross library.

Increase swap size in WSL

In windows command prompt,

cd ~

notepad .wslconfig

[wsl2]
memory=16GB
swap=64GB
swapFile=D:\\swap.vhdx

Then, type

wsl --shutdown

to shutdown the Linux and wait for at least 8 seconds.

Remove Windows paths in WSL

In WSL,

sudo vi /etc/wsl.conf

[interop]
appendWindowsPath = false

In windows command prompt,

wsl --shutdown to restart the Linux

echo $PATH

to verify the path is correct

aircrack-ng and hashcat

Mac changer:

sudo macchanger --mac=12:34:56:78:9a:bc wlan0   

 

Start monitor mode:

sudo airmon-ng start wlan0

 

Get bssid:

sudo airodump-ng wlan0mon

 

Dump handshake packet (channel = 7, bssid=aa:bb:cc:dd:ee):

sudo airodump-ng -c 7 --bssid aa:bb:cc:dd:ee:ff -w test wlan0mon

 

Deauth target:

sudo aireplay-ng -0 10 -a aa:bb:cc:dd:ee:ff -c 11:22:33:44:55:66 wlan0mon

 

Aircrack by dictionary:

sudo aircrack -w ~/pw/pw_list.txt ~/test.cap

Convert to hc22000 format

https://hashcat.net/cap2hashcat/

Hashcat by dictionary:

hashcat -m 22000 test.hc22000 ~/pw/pw_list.txt

Hashcat by brute force:

For example, 8 lowercase character,

increment rule:-i --increment-min 8 --increment-max 12

hashcat -a3 -m 22000 -i test.hc22000  ?l?l?l?l?l?l?l?l

 

Hashcat by custom pattern mixed with dictionary:

hashcat -m 22000 -i -a 6 test.hc22000 ~/pw/pw_list.txt ?d?d?d?d

Generate function call-graph by valgrind

sudo apt install kcachegrind valgrind 

Build compiler flags:

CFLAGS / CPPFLAGS: -g (or -ggdb3 -O0)

# Generate a callgrind.out.<PID> file.
valgrind --tool=callgrind ./main

 # Generate the callgrind.out.<PID> files per thread.
valgrind --tool=callgrind --separate-threads=yes  ./main

# Open a GUI tool to visualize call graph
kcachegrind callgrind.out.<PID>

Use lcov to view the coverage

Assume main.c and x.c are the source files.

1) Add CFLAGS / CPPFLAG -fprofile-arcs -ftest-coverage when build the project, .gcno is generated

2) Execute the program    #.gcda are generarted

3) gcov main.c    #main.c.gcov is generated (Optional)

4) gcov x.c    #x.c.gcov is generated (Optional)

5) Gen html report

lcov -c --directory . --output-file main_coverage.info
genhtml main_coverage.info --output-directory out

Vitis HLS FIFO interface

Xilinx Example - proj_filter_scalar:

void filter(data_t &x, coef_t coef[TAP], sum_t &y)
{
#pragma HLS INTERFACE ap_fifo port=x
#pragma HLS INTERFACE ap_fifo port=y
#pragma HLS INTERFACE ap_fifo port=coef
#pragma HLS PIPELINE II=4

//.....

}

After csynth,

Latency (cycles) = 6

Top function Arguments

x in ap_int<165>&

coef in ap_int<16>*

y out ap_int<34>&

read_from_fifo:  x_read and x_dout change at the same clock edge

write_to_fifo: y_in delay 1 clock cycle after y_write 

ready_state:  ap_ready delay 1 cycle after ap_done

Xilinx Vitis HLS Tcl script

Run Tcl script by Vitis HLS

vitis_hls -f (example).tcl

run_hls.tcl

# Create a project
open_project -reset proj_filter_scalar

# Add design files
add_files filter_scalar.cpp
# Add test bench & files
add_files -tb filter_scalar_test.cpp
add_files -tb result.golden.dat

# Set the top-level function
set_top filter

# ########################################################
# Create a solution
open_solution -reset solution1
# Define technology and clock rate
set_part  {xcvu9p-flga2104-2-i}
create_clock -period 3

# Source x_hls.tcl to determine which steps to execute
source x_hls.tcl
csim_design

if {$hls_exec == 1} {
    # Run Synthesis and Exit
    csynth_design
    
} elseif {$hls_exec == 2} {
    # Run Synthesis, RTL Simulation and Exit
    csynth_design
    
    cosim_design
} elseif {$hls_exec == 3} {
    # Run Synthesis, RTL Simulation, RTL implementation and Exit
    csynth_design
    cosim_design
    export_design -rtl verilog -flow impl
} else {
    # Default is to exit after setup
    csynth_design
}

exit

x_hls.tcl

#
# Copyright 2020 Xilinx, Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#   http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.

# Set to 0: to run setup
# Set to 1: to run setup and synthesis
# Set to 2: to run setup, synthesis and RTL simulation
# Set to 3: to run setup, synthesis, RTL simulation and RTL synthesis
# Any other value will run setup only
 
set hls_exec 1

Zynq: Build Your Own Petalinux

Prerequisite

sudo apt install gcc git make net-tools libncurses5-dev tftpd zlib1g-dev libssl-dev flex bison libselinux1 gnupg wget diffstat chrpath socat xterm autoconf libtool tar unzip texinfo zlib1g-dev gcc-multilib build-essential libsdl1.2-dev libglib2.0-dev zlib1g:i386 screen pax gzip gawk
 

Install FTP server

sudo apt install tftpd-hpa
service tftpd-hpa restart
Service tftpd-hpa status

Download and Install Petalinux (v2020.2)

Download petalinux installer from official Xilinx web site

chmod +x (installer)

mkdir -p ~/petalinux/2020.2

(installer) -d ~/petalinux/2020.2

Change to Use Bash Shell Script

chsh -s /bin/bash

# Logout and log back in after to observe the sh is changed
 

Environment Check and Setup

source ~/petalinux/2020.2/setting.sh

# Ensure working environment has been set

echo $PETALINUX

Minimum Hardware Requirement

One TTC (Triple Timer Counter)

External Memory Controller with at least 32MB of memory

UART

QSPI / SD Card

System user dts location (connect with additional peripheral?)

my-petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi

Create and Build the Project

cd ~

petalinux-create --type project --template zynq --name my-petalinux

cd my-petalinux

# Config from xsa

petalinux-config --get-hw-description=(path-containing-xsa)

# Build the package

petalinux-build

# Generate Boot Image

petalinux-package --boot --fsbl images/linux/zynq_fsbl.elf --fpga images/linux/system_wrapper.bit --u-boot

 

Prepare the SD Card

Use fdisk to assign

• 1st partition as W95 FAT32 (Partition Code: b) primary partition, 2048-50000 = ~24MB
• 2nd partition as EXT4, primary partition
  

sudo fdisk /dev/sd(?)

n = new partition

d = delete partition

t = change partition type (Code)

w = apply changes

a = active partition

mkfs.vfat -F32 vfat /dev/sd(?)1

mkfs.ext4 /dev/sd(?)2

Test U-Boot and Linux Kernel

Copy BOOT.BIN, image.ub and boot.scr into SD card FAT32 partition

Copy rootfs.cpio into EXT4 partition

Make sure the SD jumper is selected

Press reset button, output message will be shown on serial console

U-Boot 2020.01 (Mar 17 2021 - 16:35:57 +0000)                                   
                                                                                
CPU:   Zynq 7z010                                                               
Silicon: v3.1                                                                   
DRAM:  ECC disabled 512 MiB                                                     
Flash: 0 Bytes                                                                  
NAND:  0 MiB                                                                    
MMC:   mmc@e0100000: 0

=====================

Found U-Boot script /boot.scr                                                   
2010 bytes read in 12 ms (163.1 KiB/s)

===================== 

Starting kernel ...                                                             
                                                                                
Booting Linux on physical CPU 0x0                                               
Linux version 5.4.0-xilinx-v2020.2 (oe-user@oe-host) (gcc version 9.2.0 (GCC)) 1
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d                 
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache        
OF: fdt: Machine model: xlnx,zynq-7000                                          
earlycon: cdns0 at MMIO 0xe0000000 (options '115200n8')                         
printk: bootconsole [cdns0] enabled                                             
Memory policy: Data cache writealloc                                            
cma: Reserved 16 MiB at 0x1f000000 

Remarks:

BOOT.BIN:

• fsbl.elf (First stage bootloader)
• u-boot.elf (Second stage bootloader)
• design.bit (FPGA bitstream)

image.ub

• system.dtb
• uImage
• rootfs