Xilinx Vitis HLS Tcl script

Run Tcl script by Vitis HLS

vitis_hls -f (example).tcl

run_hls.tcl

# Create a project
open_project -reset proj_filter_scalar

# Add design files
add_files filter_scalar.cpp
# Add test bench & files
add_files -tb filter_scalar_test.cpp
add_files -tb result.golden.dat

# Set the top-level function
set_top filter

# ########################################################
# Create a solution
open_solution -reset solution1
# Define technology and clock rate
set_part  {xcvu9p-flga2104-2-i}
create_clock -period 3

# Source x_hls.tcl to determine which steps to execute
source x_hls.tcl
csim_design

if {$hls_exec == 1} {
    # Run Synthesis and Exit
    csynth_design
    
} elseif {$hls_exec == 2} {
    # Run Synthesis, RTL Simulation and Exit
    csynth_design
    
    cosim_design
} elseif {$hls_exec == 3} {
    # Run Synthesis, RTL Simulation, RTL implementation and Exit
    csynth_design
    cosim_design
    export_design -rtl verilog -flow impl
} else {
    # Default is to exit after setup
    csynth_design
}

exit

x_hls.tcl

#
# Copyright 2020 Xilinx, Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#   http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.

# Set to 0: to run setup
# Set to 1: to run setup and synthesis
# Set to 2: to run setup, synthesis and RTL simulation
# Set to 3: to run setup, synthesis, RTL simulation and RTL synthesis
# Any other value will run setup only
 
set hls_exec 1