Vitis HLS FIFO interface

Xilinx Example - proj_filter_scalar:

void filter(data_t &x, coef_t coef[TAP], sum_t &y)
{
#pragma HLS INTERFACE ap_fifo port=x
#pragma HLS INTERFACE ap_fifo port=y
#pragma HLS INTERFACE ap_fifo port=coef
#pragma HLS PIPELINE II=4

//.....

}

After csynth,

Latency (cycles) = 6

Top function Arguments

x in ap_int<165>&

coef in ap_int<16>*

y out ap_int<34>&

read_from_fifo:  x_read and x_dout change at the same clock edge

write_to_fifo: y_in delay 1 clock cycle after y_write 

ready_state:  ap_ready delay 1 cycle after ap_done

Xilinx Vitis HLS Tcl script

Run Tcl script by Vitis HLS

vitis_hls -f (example).tcl

run_hls.tcl

# Create a project
open_project -reset proj_filter_scalar

# Add design files
add_files filter_scalar.cpp
# Add test bench & files
add_files -tb filter_scalar_test.cpp
add_files -tb result.golden.dat

# Set the top-level function
set_top filter

# ########################################################
# Create a solution
open_solution -reset solution1
# Define technology and clock rate
set_part  {xcvu9p-flga2104-2-i}
create_clock -period 3

# Source x_hls.tcl to determine which steps to execute
source x_hls.tcl
csim_design

if {$hls_exec == 1} {
    # Run Synthesis and Exit
    csynth_design
    
} elseif {$hls_exec == 2} {
    # Run Synthesis, RTL Simulation and Exit
    csynth_design
    
    cosim_design
} elseif {$hls_exec == 3} {
    # Run Synthesis, RTL Simulation, RTL implementation and Exit
    csynth_design
    cosim_design
    export_design -rtl verilog -flow impl
} else {
    # Default is to exit after setup
    csynth_design
}

exit

x_hls.tcl

#
# Copyright 2020 Xilinx, Inc.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#   http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.

# Set to 0: to run setup
# Set to 1: to run setup and synthesis
# Set to 2: to run setup, synthesis and RTL simulation
# Set to 3: to run setup, synthesis, RTL simulation and RTL synthesis
# Any other value will run setup only
 
set hls_exec 1

HLS Important Notes

Vivado CLI execute Tcl script

vivado_hls -f script.tcl

Vivado CLI interactive mode

vivado_hls -i [-l <logfile>]

if not specific the clock uncertainty, default value is 12.5% 

Tcl script example

## Tcl script example from Xilinx Introduction to High-Level Snthesis

open_project my.prj

set_top dct

add_files dct.cpp

add_files -tb dct_test.cpp

add_files -tb in.dat

add_files -tb out.golden.dat

open_solution "solution1"

set_part {xc7k160tfbg848-1}

create_clock -period 10

source "./my.prj/solution1/directives.tcl"

csynth_design

 

Unsupported C Language Constructs

system call (e.g. printf, system, time...etc)

dynamic memory & functions (.e.g. malloc, new)

virtual function

pointer casting

recursive function

Most of STL library which contains recursive and dynamic allocation

Important Notes

Use APCC to compile the intN data type, gcc doesn't support this data type

Must be care if use access pointer with the same function multiple time

 

 

 

High Level Synthesis by using Xilinx Vitis

// Analyze the Xilinx Vitis example

 

// C General include header file

#include <ap_cint.h>

// C typedefs for top-level input and output int / fixed-point formats

// [u]int<precision> (1024 bits) 

typedef int7 in_data_t;

typedef uint7 in_data_t;

// C++ General include header file

// ap_[u]int<W> (1024 bits)
// ap_[u]fixed<W,I,Q,O,N> 

#include <ap_int.h>

#include <ap_fixed.h>

#include <hls_stream.h>

// C++ typedefs for top-level input and output int / fixed-point formats

typedef ap_ufixed<IN_BW,IN_IW> in_data_t;

typedef ap_ufixed<OUT_BW,OUT_IW> out_data_t;

typedef ap_uint<IN_BW> data_t;

typedef ap_int<18> dout1_t;

typedef ap_uint<13> dout2_t;

typedef ap_ufixed<10,8, AP_RND, AP_SAT> din1_t;

typedef ap_fixed<36,30> dout_t;

hls::stream<uint8_t> &bytes_in,

// Support array

typedef ap_int<7> din_t;

typedef ap_int<10> dout_t;

dout_t mem_bottleneck_resolved(din_t mem[N]) {

}