Vitis HLS FIFO interface

Xilinx Example - proj_filter_scalar:

void filter(data_t &x, coef_t coef[TAP], sum_t &y)
{
#pragma HLS INTERFACE ap_fifo port=x
#pragma HLS INTERFACE ap_fifo port=y
#pragma HLS INTERFACE ap_fifo port=coef
#pragma HLS PIPELINE II=4

//.....

}

After csynth,

Latency (cycles) = 6

Top function Arguments

x in ap_int<165>&

coef in ap_int<16>*

y out ap_int<34>&

read_from_fifo:  x_read and x_dout change at the same clock edge

write_to_fifo: y_in delay 1 clock cycle after y_write 

ready_state:  ap_ready delay 1 cycle after ap_done